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lt3743 1 3743fb typical application description high current synchronous step-down led driver with three-state control the lt ? 3743 is a ? xed frequency synchronous step-down dc/dc controller designed to drive high current leds. the average current mode controller will maintain inductor current regulation over a wide output voltage range of 0v to (v in C 2v). led dimming is achieved through analog dimming on the ctrl_l, ctrl_h and ctrl_t pins and with pwm dimming on the pwm and ctrl_sel pins. through the use of externally switched load capacitors, the lt3743 is capable of changing regulated led current levels within several s, providing accurate, high speed pwm dimming between two current levels. the switching frequency is programmable from 200khz to 1mhz through an external resistor on the rt pin. additional features include voltage regulation and overvoltage protection set with a voltage divider from the output to the fb pin. overcurrent protection is provided and set by the ctrl_h pin. 92% ef? cient 20a led driver features applications n pwm dimming provides up to 3000:1 dimming ratio n ctrl_sel dimming provides up to 3000:1 dimming ratio between any current n three-state current control for color mixing n 6% current regulation accuracy n 6v to 36v input voltage range n average current mode control n 2s maximum recovery time between any current regulation state n <1a shutdown current n output voltage regulation and open-led protection n thermally enhanced 4mm 5mm qfn and 28-pin fe package n dlp projectors n high power architectural lighting n laser diodes en/uvlo pwm ctrl_sel en/uvlo pwm ctrl_sel hg v in cboot v ref ctrl_l ctrl_h ctrl_t lt 3 7 4 3 rt sync sw lg gnd vch vcl sense + sense C pwmgh pwmgl v cc_int 220nf 1.1h 22f 330f s 3 2.5m fb 10nf 34k 8.2nf 34k 8.2nf 82.5k 100k 100k 330f s 3 51.1k 3743 ta01a 10.0k 4.7f 330f s 3 2.2nf r ntc 10k 4.7f s 4 v in 10v to 30v output 20a maximum 1f m1 m2 ss r hot 499 m3 m4 m1, m2: sir462dp m3, m4: si7234dp ctrl_sel 5v/div pwm 5v/div sw 20v/div i led 10a/div 20s/div 3743 ta01b v in = 24v 0a to 2a to 20a led current step l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and true color pwm is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 7199560, 7321203 and others pending.
lt3743 2 3743fb v in voltage ................................................................40v en/uvlo voltage ........................................................6v v ref voltage ................................................................3v ctrl_l, ctrl_h, ctrl_t voltage ............................3v pwm, ctrl_sel voltage ...........................................6v sense + voltage ........................................................40v sense C voltage ........................................................40v vch, vcl voltage .......................................................3v sw voltage ...............................................................40v (note 1) order information lead free finish tape and reel part marking* package description temperature range lt3743eufd#pbf lt3743eufd#trpbf 3743 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3743iufd#pbf lt3743iufd#trpbf 3743 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3743efe#pbf lt3743efe#trpbf lt3743fe 28-lead plastic tssop C40c to 125c lt3743ife#pbf lt3743ife#trpbf lt3743fe 28-lead plastic tssop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ absolute maximum ratings 9 10 top view ufd package 28-lead (4mm s 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 gnd en/uvlo v ref ctrl_t gnd ctrl_h ctrl_l ss pwmgl gnd gnd pwmgh pwm ctrl_sel sync rt v in v cc_int lg cboot sw hg gnd fb sense + sense C vcl vch 7 17 18 19 20 21 22 16 8 15 29 gnd t jmax = 125c, ja = 37c/w exposed pad (pin 29) is gnd, must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc_int gnd v in en/uvlo v ref ctrl_t gnd ctrl_h ctrl_l ss gnd fb sense + sense C lg gnd cboot sw hg pwmgl gnd pwmgh pwm ctrl_sel sync rt vch vcl 29 gnd t jmax = 125c, ja = 30c/w exposed pad (pin 29) is gnd, must be soldered to pcb pin configuration cboot ......................................................................46v rt voltage...................................................................3v fb voltage ...................................................................3v ss voltage ..................................................................6v sync voltage ..............................................................6v storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) tssop .............................................................. 300c (note 2)
lt3743 3 3743fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 12v, v en/uvlo = 5v, v sync = 0v, v ctrl_sel = 0v, v pwm = 2v, unless otherwise noted. parameter conditions min typ max units input voltage range 636v v in pin quiescent current (note 3) non-switching operation shutdown mode v pwm = v ctrl_sel = 0v, not switching, r t = 40k v en/uvlo = 0v l 1.8 0.1 2.5 1 ma a en/uvlo pin falling threshold 1.49 1.55 1.61 v en/uvlo hysteresis 130 mv en/uvlo pin current v in = 6v, en/uvlo = 1.45v 5.5 a pwm pin threshold 1.0 v ctrl_sel threshold 1.0 v sync pin threshold 1.0 v ctrl_h and ctrl_l pin control range 0 1.5 v ctrl_h and ctrl_l pin current 100 na reference reference voltage (v ref pin) l 1.96 2 2.04 v inductor current sensing full range sense + to sense C v ctrl_h = 1.5v, v sense C = 6v l 48 51 54 mv sense + pin current v sense + = v sense C = 6v 50 na sense C pin current v sense + = v sense C = 6v 10 a internal v cc regulator (v cc_int pin) regulation voltage l 4.7 5 5.2 v nmos fet driver (note 2) non-overlap time hg to lg 100 ns non-overlap time lg to hg 60 ns minimum on-time lg (note 3) 50 ns minimum on-time hg (note 3) 80 ns minimum off-time lg (note 3) 60 ns high side driver switch on-resistance gate pull up gate pull down v cboot C v sw = 5v 2.3 1.3 low side driver switch on-resistance gate pull up gate pull down v cc_int = 5v 2.5 1.3 switching frequency f sw r t = 40k r t = 200k l 900 190 1000 200 1070 233 khz khz soft-start charging current 5.5 a voltage regulation ampli? er input bias current 1na g m 200 a/v feedback regulation voltage v ctrl_h = 0v, v ctrl_l = 2v, v sense + = 2v, i sense C = 14a l 0.945 1 1.025 v
lt3743 4 3743fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 12v, v en/uvlo = 5v, unless otherwise noted. parameter conditions min typ max units pwmg control signals ctrl_sel high to pwmgl low delay 10 40 ns ctrl_sel high to pwmgh high delay 150 200 ns ctrl_sel low to pwmgh low delay 30 60 ns ctrl_sel low to pwmgl high delay 170 220 ns pwmgh and pwmgl pull-up impedance 3.2 pwmgh and pwmgl pull-down impedance 1.75 current control loop g m amp offset voltage v sense + = 4v, v sense C = 4v l C3 0 3 mv input common mode range v cm(low) v cm(high) v cm(high) measured from v in to v cm 0 2 v v output impedance 3.5 m g m 375 475 625 a/v differential gain 1.7 v/mv note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3743e is guaranteed to meet performance speci? cations from 0c to 125c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3743i is guaranteed to meet performance speci? cations over the C40c to 125c operating junction temperature range. note 3: the minimum on and off times are guaranteed by design and are not tested.
lt3743 5 3743fb typical performance characteristics en/uvlo threshold (falling) en/uvlo pin current i q in shutdown v in (v) 6 en/uvlo threshold (v) 1.58 1.64 1.70 30 C50c 130c 3743 g01 1.52 1.46 1.40 12 18 24 36 v in (v) 6 en/uvlo pin current (a) 6 8 10 30 3743 g02 4 2 0 12 18 24 36 25c 130c C50c v in (v) 0 i q (a) 0.3 0.4 0.5 32 3743 g03 0.2 0.1 0 8 16 24 40 130c 25c quiescent current (non-switching) v ref pin voltage v ref current limit v in (v) 6 quiescent current (ma) 1.2 1.6 2.0 30 3743 g04 0.8 0.4 0 12 18 24 36 t a = 25c t a = 130c t a = C50c temperature (c) C50 v ref voltage (v) 2.00 2.01 2.02 90 3743 g05 1.99 1.98 1.97 C15 20 55 125 v in = 36v v in = 6v v in (v) 6 i limit (ma) 1.2 1.4 1.6 30 3743 g06 1.0 0.8 12 18 24 36 t a = 25c t a = 130c t a = C50c oscillator frequency rt pin current limit soft-start pin current temperature (c) C50 frequency (mhz) 0.9 1.2 1.5 90 3743 g07 0.6 0.3 0 C15 20 55 125 1.2mhz 900khz 220khz temperature (c) C50 i limit (a) 70 80 90 90 3743 g08 60 50 40 C15 20 55 125 temperature (c) C50 i ss (a) 5 6 7 90 3743 g09 4 3 C15 20 55 125 v in = 36v v in = 6v
lt3743 6 3743fb typical performance characteristics v cc_int load reg at 12v regulated current vs v fb open-led threshold open-led timeout regulated sense voltage common mode lockout internal uvlo cboot-sw uvlo voltage v cc_int uvlo temperature (c) C50 v in (v) 4.0 4.5 5.0 90 3743 g10 3.5 3.0 C15 20 55 125 temperature (c) C50 1.50 voltage (v) 1.75 2.00 2.25 2.50 2.75 3.00 C15 20 55 90 3743 g11 125 temperature (c) C50 2.50 uvlo (v) 2.75 3.00 3.25 3.50 3.75 4.00 C15 20 55 90 3743 g12 125 i load (ma) 0 v cc_int (v) 5.2 5.6 6.0 40 3743 g13 4.8 4.4 4.0 10 20 30 60 50 v fb (mv) 800 0 control current (%) 20 40 60 80 100 120 850 900 950 1000 3743 g14 1050 C50c 125c temperature (c) C50 open-led threshold (v) 1.3 1.4 1.5 90 3743 g15 1.2 1.1 1.0 C15 20 55 125 temperature (c) C50 open-led timeout (s) 15 17 19 90 3743 g16 13 11 9 C15 20 55 125 v ctrl (v) 0 0 v sense + C v sense C (mv) 10 20 30 40 50 60 0.5 1.0 1.5 3743 g17 2.0 temperature (c) C50 cm lockout (v) 1.5 2.0 2.5 90 3743 g18 1.0 0.5 0 C15 20 55 125 v in = 6v v in = 36v measured v in C v out
lt3743 7 3743fb typical performance characteristics non-overlap pwm signal delay non-overlap time minimum on-time minimum off-time regulation accuracy ctrl_h = 1.5v, v in = 12v regulation accuracy ctrl_h = 0.75v, v in = 12v pwm driver r ds(0n) hg driver r ds(on) lg driver r ds(on) temperature (c) C50 r ds(on) () 3 4 5 90 3743 g19 2 1 0 C15 20 55 125 pmos nmos temperature (c) C50 r ds(on) () 3 4 5 90 3743 g20 2 1 0 C15 20 55 125 pmos nmos temperature (c) C50 r ds(on) () 3 4 5 90 3743 g21 2 1 0 C15 20 55 125 pmos nmos temperature (c) C50 delay (ns) 130 140 150 90 3743 g22 120 110 100 C15 20 55 125 pwmgl to pwmgh pwmgh to pwmgl temperature (c) C50 non-overlap time (ns) 90 120 150 90 3743 g23 60 30 0 C15 20 55 125 hg to lg lg to hg temperature (c) C50 minimum on-time (ns) 90 120 150 90 3743 g24 60 30 0 C15 20 55 125 hg lg temperature (c) C50 minimum off-time (ns) 180 240 300 90 3743 g25 120 60 0 C15 20 55 125 hg lg output voltage (v) 0 C3 accuracy (%) C2 C1 0 1 2 3 2.5 5.0 7.5 10 3743 g26 output voltage (v) 0 C6 accuracy (%) C4 C2 0 2 4 6 2.5 5.0 7.5 10 3743 g27
lt3743 8 3743fb typical performance characteristics led current waveforms (3000:1) 2a to 20a led current waveforms (3000:1) 0a to 2a to 20a led current waveforms (3000:1) analog dimming on ctrl_l c out(low) = 22f, c out(high) = 1mf overcurrent threshold led current waveforms (90% pwm) 0.5a to 5a led current waveforms (2000:1) 3a to 10a voltage regulation with 10a regulated inductor current common mode lockout (v in = 7v) overvoltage lockout operation with open-load condition ctrl_h (v) 0 0 v sense + C v sense C (mv) 20 40 60 80 100 120 0.75 1.5 2.25 3.0 3743 g28 ctrl_sel 5v/div sw 20v/div i led 5a/div i l 10a/div 40s/div 3743 g29 ctrl_sel 5v/div i led 5a/div i l 10a/div 5s/div 3743 g30 ctrl_sel 5v/div sw 10v/div pwm 5v/div i led 10a/div 20s/div 3743 g32 ctrl_l 0.2v/div ctrl_sel 5v/div pwm 5v/div i led 8a/div 40s/div 3743 g33 v out 2v/div i l 5a/div 100s/div 3743 g34 v out 2v/div i l 200ma/div 1ms/div 3743 g35 v out 2v/div i l 200ma/div 40ms/div 3743 g36 ctrl_sel 5v/div sw 10v/div i led 11.1a/div 20s/div 3743 g31
lt3743 9 3743fb pin functions (qfn/tssop) gnd (pins 1, 5, 9, 20, 21, exposed pad pin 29/pins 2, 7, 11, 22, 27, exposed pad pin 29): ground. the exposed pad must be soldered to the pcb. en/uvlo (pin 2/pin 4): enable pin. the en/uvlo pin acts as an enable pin and turns on the internal current bias core and subregulators at 1.55v. the pin does not have any pull-up or pull-down, requiring a voltage bias for normal part operation. full shutdown occurs at approximately 0.5v. v ref (pin 3/pin 5): buffered 2v reference capable of 0.5ma drive. ctrl_t (pin 4/pin 6): the thermal control input to reduce the regulated current level for both current levels (ctrl_l and ctrl_h). ctrl_h (pin 6/pin 8): the ctrl_h pin sets the high level regulated output current and overcurrent. the maximum input voltage is internally clamped to 1.5v. the overcurrent set point is equal to the high level regulated current level set by the ctrl_h pin with an additional 23mv offset between the sense + and sense C pins. ctrl_l (pin 7/pin 9): the ctrl_l pin sets the low level regulated output current. it is not recommended that the ctrl_l voltage be higher than the ctrl_h voltage. ss (pin 8/pin 10): soft-start pin. place an external capaci- tor to ground to limit the regulated current during start-up conditions. the ss pin has a 5.5a charging current. this pin controls both of the regulated inputs determined by ctrl_l and ctrl_h. fb (pin 10/pin 12): feedback pin for overvoltage protec- tion. the feedback voltage is 1v. overvoltage/open led is sensed through the fb pin. when the feedback voltage exceeds 1.3v, the overvoltage lockout prevents switching and connects both output capacitors to discharge the inductor current. sense + (pin 11/pin 13): sense + is the inverting input of the average current mode loop error ampli? er. this pin is connected to the external current sense resistor, r s . the voltage drop between sense + and sense C referenced to the voltage drop across an internal resistor produces the input voltages to the current regulation loop. sense C (pin 12/pin 14): sense C is the noninverting input of the average current mode loop error ampli? er. the refer- ence current, based on ctrl_l or ctrl_h ? ows out of the pin to the output (led) side of the sense resistor, r s . vcl (pin 13/pin 15): vcl provides the necessary compen- sation for the average current loop stability during low level current regulation. typical compensation values are 15k to 80k for the resistor and 2nf to 10nf for the capacitor. vch (pin 14/pin 16): vch provides the necessary com- pensation for the average current loop stability during high level current regulation. typical compensation values are 15k to 80k for the resistor and 2nf to 10nf for the capacitor. rt (pin 15/pin 17): a resistor to ground sets the switching frequency between 200khz and 1mhz. when using the sync function, set the frequency to be 20% lower than the sync pulse frequency. this pin is current limited to 60a. do not leave this pin open. sync (pin 16/pin 18): frequency synchronization pin. this pin allows the switching frequency to be synchronized to an external clock. the r t resistor should be chosen to operate the internal clock at 20% slower than the sync pulse frequency. the synchronization range is 240khz to 1.2mhz. this pin should be grounded when not in use. ctrl_sel (pin 17/pin 19): the ctrl_sel pin selects between the high current control, ctrl_h and the low current control, ctrl_l. when high, the vch pin is connected to the error amp output and the pwmgh gate signal is high. when low, the vcl pin is connected to the error amp output and the pwmgl gate signal is high. this pin is used for current level dimming of the led. this pin should be grounded when not in use. pwm (pin 18/pin 20): the input pin for pwm dimming of the led. when low, all switching is terminated and the output caps are disconnected. this pin should be pulled to v cc_int when not in use. pwmgh (pin 19/pin 21): the pwmgh output pin drives the gate of an external fet to connect one of the switching regulator output capacitors to the load. the driver pull-up impedance is 3.2 and pull-down impedance is 1.75.
lt3743 10 3743fb pwmgl (pin 22/pin 23): the pwmgl output pin drives the gate of an external fet to connect one of the switching regulator output capacitors to the load. the driver pull-up impedance is 3.2 and pull-down impedance is 1.75. hg (pin 23/pin 24): hg is the top fet gate drive signal that controls the state of the high side external power fet. the driver pull-up impedance is 2.3 and pull-down impedance is 1.3. sw (pin 24/pin 25): the sw pin is used internally as the lower rail for the ? oating high side driver. externally, this node connects the two power fets and the inductor. cboot (pin 25/pin 26): the cboot pin provides a ? oat- ing 5v regulated supply for the high side fet driver. an external schottky diode is required from the v cc_int pin to the cboot pin to charge the c boot capacitor when the switch pin is near ground. pin functions (qfn/tssop) lg (pin 26/pin 28): lg is the bottom fet gate drive sig- nal that controls the state of the low side external power fet. the driver pull-up impedance is 2.5 and pull-down impedance is 1.3. v cc_int (pin 27/pin 1): a regulated 5v output for charging the c boot capacitor. v cc_int also provides the power for the digital and switching subcircuits. below 6v v in , tie this pin to the rail. v cc_int is current limited to 50ma. shutdown operation disables the output voltage drive. v in (pin 28/pin 3): input supply pin. must be locally bypassed with a 1f low esr capacitor to ground.
lt3743 11 3743fb block diagram C + C + pwm comparator high side driver cboot hg sw lg 3k low side driver rq s g m amp g m = 475a/v r o = 3.5m i out = 40a oscillator 2v reference 5.5a 90k 1.5v current mirror sync rt 16 ctrl_h 6 ctrl_l ctrl buffer voltage regulator amp open-led comparator 7 ss 8 vcl 13 vch 14 ctrl_sel 17 pwm 18 ctrl_t 4 v ref 3 en/uvlo v in 2 25 v cc_int 27 v in 28 23 24 26 sense + 15 syncronous controller internal regualtor and uvlo 2.2nf 100nf 8.2nf 47f 0.1f 330f 3 33nf 330f 3 10a led 10 2.2h r s 5m output 10f v in sync 402k 133k 82.5k C + C + 11 sense C 12 fb 10 pwmgl C + + + 10k 1v 1.3v 2.5 2.5 40.2k 34k 8.2nf 34k 22 pwmgh 3743 f01 19 10 figure 1. block diagram (qfn package)
lt3743 12 3743fb operation the lt3743 utilizes ? xed frequency, average current mode control to accurately regulate the inductor current, independently from the output voltage. this is an ideal solution for applications requiring a regulated current source including driving high current leds where the forward junction voltage can range from 2v to 6v with a dynamic resistance of 20m to 40m. the control loop will regulate the current in the inductor at an accuracy of 6%. for additional operation information, refer to the block diagram in figure 1. the control loop has two independent reference inputs, determined by the analog control pins, ctrl_h and ctrl_l. when the ctrl_sel pin is low, the control loop uses the reference determined by the ctrl_l pin and when high, the loop uses the reference determined by the ctrl_h pin. the analog voltage at the ctrl_l and ctrl_h pins is buffered and produces a reference volt- age across an internal resistor. the internal buffers have a 1.5v clamp on the output, limiting the analog control range of the ctrl_l and ctrl_h pins from 0v to 1.5v. the average current mode control loop uses the internal reference voltage to regulate the inductor current, as a voltage drop across the external sense resistor, r s . in many applications, a rapid transition between the two regulated current states is desirable to provide background led color mixing for pure colors in an rgb projector or display. for this purpose, pulse width modulation dimming can be achieved with both the pwm and ctrl_sel pins. when the pwm pin is low, the regulated current in the inductor is zero and both output capacitors are discon- nected. when the pwm pin is high, and the ctrl_sel pin is low, the regulated current in the inductor is determined by the analog voltage at the ctrl_l pin. when the pwm and ctrl_sel pins are both high, the regulated current in the inductor is determined by the analog voltage at the ctrl_h pin. the lt3743 uses a unique switched output capacitor topology and two independent compensation networks to transition between the two regulated current states in less than 2s. when the ctrl_sel pin is low and the pwm pin is high, the pwmgl output pin is high, switch- ing in the output capacitor for the ctrl_l current level. the ctrl_l output capacitor stores the led forward voltage drop when the control loop regulates the low cur- rent level. when the ctrl_sel pin changes to the high state, a 150ns delay ensures that the output capacitors are not connected at the same time. after this delay, the output capacitor for the ctrl_h level is switched in when pwmgh goes high and immediately delivers current to the led. the ctrl_h output capacitor has the voltage drop of the led with the regulated current determined by the analog voltage at the ctrl_h pin. to achieve minimum transition delay, the inductor is precharged to 70% of the regulation current level just after the pwmgh pin goes high. conversely, when the pwm pin goes low, the induc- tor is discharged to 70% of the low current level before normal switching at the low current level commences. the error ampli? er for the average current mode control loop also has a common mode lockout that regulates the inductor current so that the error ampli? er is never oper- ated out of the common mode range. the common mode range is with an output voltage from 0v to 2v below the v in supply rail. the overcurrent set point is equal to the high level regulated current level set by the ctrl_h pin with an additional 23mv offset between the sense + and sense C pins. the overcurrent is limited on a cycle-by-cycle basis; shutting switching down once the overcurrent level is reached. overcurrent is not soft started. the output voltage may be limited with a resistor divider from the output back to the fb pin. the reference at the fb pin is 1.0v. if the output voltage level is high enough to engage the voltage loop, the regulated inductor current will be reduced so that the output voltage is limited. if the voltage at the fb pin reaches 1.3v (30% higher than the regulation level), an internal open-led ? ag is set, shutting down switching for 13s and switching in both output capacitors to fully drain the inductors current. during start-up, the ss pin is held low until the ? rst time the pwm pin goes high. once the pwm signal goes high, the capacitor at the ss pin is charged with a 5.5a current source. the internal buffers for the ctrl_l and ctrl_h signals are limited by the voltage at the ss pin, slowly ramping the regulated inductor current to the current de- termined by the voltage at the ctrl_h or ctrl_l pins.
lt3743 13 3743fb applications information programming inductor current the analog voltage at the ctrl_l and ctrl_h pins is buffered and produces a reference voltage, v ctrl , across an internal resistor. the regulated average inductor current is determined by: i v r o ctrl s = 30 ? where r s is the external sense resistor and i o is the aver- age inductor current, which is equal to the led current. figure 2 shows the led current vs r s . the maximum power dissipation in the resistor will be: p v r rs s = () 005 2 . table 1 contains several resistors values, the correspond- ing maximum current and power dissipation in the sense resistor. figure 3 shows the power dissipation in r s . table 1. sense resistor values maximum led current (a) resistor, r s (m) power dissipation (w) 1 50 0.05 5 10 0.25 10 5 0.5 25 2 1.25 inductor selection the recovery time between regulated states is critical to maintaining accurate control of the led current. for this reason, sizing the inductor to have no less than 30% peak-to-peak ripple will provide excellent recovery time with reasonable ripple. the overcurrent set point is equal to the high level regulated current level set by the ctrl_h pin with an additional 23mv offset between the sense + and sense C pins. the saturation current for the inductor should be at least 20% higher than the maximum regu- lated current. the following equation sizes the inductor to achieve a reasonable recovery time while minimizing the inductor ripple: l = v in ?v f () Cv f () 2 0.2 ? f s ?i o ?v in where v f is the led forward voltage drop, i o is the maximum regulated current in the inductor and f s is the switching frequency. using this equation, the inductor will have ap- proximately 10% ripple at maximum regulated current. table 2. recommended inductor manufacturers vendor website coilcraft www.coilcraft.com sumida www.sumida.com vishay www.vishay.com wrth electronics www.we-online.com nec-tokin www.nec-tokin.com r s (m) 0 0 power dissipation (w) 0.2 0.6 0.8 1.0 1.4 2 10 14 3743 f03 0.4 1.2 8 18 20 4 6 12 16 r s (m) 0 led current (a) 10 20 30 5 15 25 4 8 12 16 3743 f02 20 2 0 6 10 14 18 figure 2. r s value selection for led current figure 3. power dissipation in r s
lt3743 14 3743fb switching mosfet selection when selecting switching mosfets, the following pa- rameters are critical in determining the best devices for a given application: total gate charge (q g ), on-resistance (r ds(on) ), gate to drain charge (q gd ), gate-to-source charge (q gs ), gate resistance (r g ), breakdown voltages (maximum v gs and v ds ) and drain current (maximum i d ). the following guidelines provide information to make the selection process easier. both of the switching mosfets need to have their maximum rated drain currents greater than the maximum inductor current. the following equation calculates the peak induc- tor current: i max = i o + v in ?v f + r d i o () Cv f + r d i o () 2 2?f s ?l?v i n where v in is the input voltage, l is the inductance value, v f is the led forward voltage drop, r d is the dynamic series resistance of the led, i o is the regulated output current and f s is the switching frequency. during mosfet selec- tion, notice that the maximum drain current is temperature dependant. most data sheets include a table or graph of the maximum rated drain current vs temperature. the maximum v ds should be selected to be higher than the maximum input supply voltage (including transient) for both mosfets. the signals driving the gates of the switching mosfets have a maximum voltage of 5v with respect to the source. during start-up and recovery con- ditions, the gate drive signals may be as low as 3v. to ensure that the lt3743 recovers properly, the maximum threshold should be less than 2v. for a robust design, select the maximum v gs greater than 7v. power losses in the switching mosfets are related to the on-resistance, r ds(on) ; the transitional loss related to the gate resistance, r g ; gate-to-drain capacitance, q gd and gate-to-source capacitance, q gs . power loss to the on-resistance is an ohmic loss, i 2 r ds(on) , and usually dominates for input voltages less than ~15v. power losses to the gate capacitance dominate for voltages greater than ~12v. when operating at higher input voltages, ef? ciency can be optimized by selecting a high side mosfet with higher r ds(on) and lower c gd . the power loss in the high side mosfet can be approximated by: p loss = (ohmic loss) + (transition loss) p loss v f + r d i o () v in ?i o 2 r ds(on) ? t + v in ?i out 5v ?q gd + q gs () ?2?r g + r pu + r pd () () ?f s where t is a temperature-dependant term of the mosfets on-resistance. using 70c as the maximum ambient operat- ing temperature, t is roughly equal to 1.3. r pd and r pu are the lt3743 high side gate driver output impedance, 1.3 and 2.3 respectively. a good approach to mosfet sizing is to select a high side mosfet, then select the low side mosfet. the trade- off between r ds(on) , q g , q gd and q gs for the high side mosfet is shown in the following example. v o is equal to 4v. comparing two n-channel mosfets, with a rated v ds of 40v and in the same package, but with 8 different r ds(on) and 4.5 different q g and q gd : m1: r ds(on) = 2.3m, q g = 45.5nc, q gs = 13.8nc, q gd = 14.4nc , r g = 1 m2: r ds(on) = 18m, q g = 10nc, q gs = 4.5nc, q gd = 3.1nc , r g = 3.5 power loss for both mosfets is shown in figure 4. observe that while the r ds(on) of m1 is eight times lower, the power loss at low input voltages is equal, but four times higher at high input voltages than the power loss for m2. another power loss related to switching mosfet selection is the power lost to driving the gates. the total gate charge, q g , must be charged and discharged each switching cycle. the power is lost to the internal ldo within the lt3743. the power lost to the charging of the gates is: p loss_ldo (v in C 5v) ? (q glg + q ghg ) ? f s where q glg is the low side gate charge and q ghg is the high side gate charge. applications information
lt3743 15 3743fb whenever possible, utilize a switching mosfet that minimizes the total gate charge to limit the internal power dissipation of the lt3743. table 3. recommended switching fets v in (v) v out (v) i d (a) top fet bottom fet manufacturer 8 4 5-10 rjk0365dpa rjk0330dpb renesas www.renesas.com 24 4 5 rjk0368dpa rjk0332dpb 24 2-4 20 rjk0365dpa rjk0346dpa 12 2-4 10 fdms8680 fdms8672as fairchild www.fairchildsemi.com 36 4 20 si7884bdp sir470dp vishay www.vishay.com 24 4 40 psmn4r0- 30yl rjk0346dpa nxp/philips www.nxp.com input capacitor selection the input capacitor should be sized at 4f for every 1a of output current and placed very close to the high side mosfet. a small 1f ceramic capacitor should be placed near the v in and ground pins of the lt3743 for optimal noise immunity. the input capacitor should have a ripple current rating equal to half of the maximum output current. it is recommended that several low esr ceramic capacitors be used as the input capacitance. use only type x5r or x7r capacitors as they maintain their capacitance over a wide range of operating voltages and temperatures. output capacitor selection the output capacitors need to have very low esr (equivalent series resistance) to allow the led current to ramp quickly. a minimum of 50f/a of load current should be used in most designs. the capacitors also need to be surge rated to the maximum output current. to achieve the lowest possible esr, several low esr capacitors should be used in parallel. many applications bene? t from the use of high density poscap capacitors, which are easily destroyed when exposed to overvoltage conditions. to prevent this, select poscap capacitors that have a voltage rating that is at least 50% higher than the regulated voltage c boot capacitor selection the c boot capacitor must be sized less than 220nf and more than 50nf to ensure proper operation of the lt3743. use 220nf for high current switching mosfets with high gate charge. applications information figure 4a. power loss example for m1 figure 4b. power loss example for m2 figure 4 input voltage (v) 0 4 5 7 30 3743 f04a 3 2 10 20 40 1 0 6 mosfet power loss (w) total ohmic transitional input voltage (v) 0 mosfet power loss (w) 1.0 1.5 40 3743 f04b 0.5 0 10 20 30 2.5 2.0 total ohmic transitional
lt3743 16 3743fb v cc_int capacitor selection the bypass capacitor for the v cc_int pin should be larger than 5f for stability and has no esr requirement. it is recommended that the esr be lower than 50m to reduce noise within the lt3743. for driving mosfets with gate charges larger than 10nc, use 0.5f/nc of total gate charge. led current dimming the lt3743 provides the capability of traditional zero to full current pwm dimming as well as pwm dimming between two regulated led current states. when the pwm signal is low, no switching occurs and the output capacitors are disconnected from ground. when pwm is high and ctrl_sel is low, the inductor current is regulated to the low current state. in this state, the pwmgl signal is high, connecting the output capacitor for the low regulated current state. when pwm and ctrl_sel are both high, the inductor current is regulated to the high current state. in this state, the pwmgh signal is high, connecting the output capacitor for the high regulated current state. the transition time between each of the regulated inductor currents is determined by the inductor size, v in and v o . due to the use of the switched output capacitors, the led current will begin to ? ow within 130ns of the transition on the ctrl_sel pin. figure 8 shows the led and inductor current waveforms with the various states of the control signals. to adjust the regulated led current for the two control states, an analog voltage is applied to the ctrl_l and ctrl_h pins. figure 6 shows the regulated voltage across the sense resistor for control voltages up to 2v. figure 7 shows the ctrl_l voltage created by a voltage divider from v ref to ground. when sizing the resistor divider, please be aware that the v ref pin is current limited to 500a. above 1.5v, the control voltage has no effect on the regulated led current. for the widest dimming range, use the highest switching frequency possible and lowest pwm frequency. for con- ? guration with the maximum pwm range, please contact factory for optimized component selection. applications information lt3743 v ref r2 r1 3743 f07 ctrl_l pwm ctrl_sel pwmgh pwmgl ictrl_h inductor current led current t on(pwm) t pwm ictrl_l 3743 f08 figure 6. led current vs ctrl voltage figure 7. analog control of led current figure 8. led current vs ctrl voltage v ctrl (v) 0 0 v sense + C v sense C (mv) 10 20 30 40 50 60 0.5 1.0 1.5 3743 f06 2.0
lt3743 17 3743fb mosfet selection for the switched output capacitors the mosfets used for the switched-output capacitor need to also handle the maximum regulated current while the capacitor is charged. the output drivers on the pwmgh and pwmgl pins have a pull-up impedance of 3.2 and a pull-down impedance of 1.75. this provides adequate gate drive for the pwm mosfets without the need for an additional gate driver. if the led forward resistance and the difference between the two regulated currents is large enough, then two mosfets are required to prevent the body diode of the mosfet from conducting and discharging the capacitor for the high current state. figure 9 shows the output capacitor for the high current regulation state discharged with the body diode when a single mosfet is used. figure 10 shows the application circuit with a drain-to-drain con? guration for the high current output capacitor. in this con? guration, the body diode of the up- per mosfet blocks conduction and prevents discharge of the high current output capacitor. if the voltage between the low state and the high state is very large (greater than the threshold of the mosfet) then the capacitor may once again be discharged. to account for this, choose a mosfet that has a threshold greater than the voltage difference. if the voltage difference exceeds 1.5v, use the circuit shown in figure 11. the circuit shown will keep the capacitor from discharging to a voltage dif- ference of approximately 2v + v th . applications information figure 9. body diode of high current fet discharges the output capacitor figure 10. with a drain-to-drain con? guration, the body diode of the top fet blocks the current path that would discharge the high current output capacitor figure 11. application for large differences in regulated currents lt3743 off 0v 3.8v 5v pwmgh 3743 f09 pwmgl 3.04v v f = 3v r d = 40m i ctrl_l = 1a i ctrl_h = 20a on lt3743 3.8v pwmgh 3743 f10 pwmgl 3.04v v f = 3v r d = 40m i ctrl_l = 1a i ctrl_h = 20a lt3743 3.01k 2k 2v v cc_int pwmgh 3743 f11 pwmgl v f = 3v r d = 200m i ctrl_l = 1a i ctrl_h = 20a board and interconnect inductance the board and interconnect inductance from the output capacitors to the load also determine the rate of change in load (led) current. the rate of change in load current will be: di dt vv l l high low board = ? where di l /dt is the rate of change in the load current, v high is the output voltage when the inductor is regulated at the high level, and v low is the output voltage when the inductor is regulated at the low state. when measuring the led current do not use a current probe. the core material used in most probes adds inductance and slows the rise time of the led current. instead, when measuring the current, use a sense resistor.
lt3743 18 3743fb applications information voltage regulation and overvoltage protection the lt3743 uses the fb pin to regulate the output to a maximum voltage and to provide a high speed overvoltage lockout to avoid high voltage conditions that may damage expensive high current leds. the regulated output voltage is programmed using a resistor divider from the output and ground (figure 12). when the output voltage exceeds 130% of the regulated voltage level (1.3v at the fb pin), the internal open-led ? ag is set, terminating switching and forcing both pwmgl and pwmgh signals high. the regulated output voltage must be greater than 2v and is set by the equation: v out = 1v 1 + r2 r1 the internal power consumption of the lt3743 is de- termined by the switching frequency, v in , and the gate charge, q g of the external switching mosfets selected. the 4mm 5mm qfn package has a ja of 35c/w. the following equation calculates the maximum switching frequency to avoid current limit and thermal shutdown at a given ambient operating temperature, t a : f ct cw v v q q f s a in ghg glg () () () + () 163 35 5 ? /? ? ? s s glg ghg ma qq + () 60 since the regulated output current ? owing into the led may be very large, the switching frequency needs to be carefully considered. higher switching frequencies will reduce the large size of high saturation current inductors, while reducing ef? ciency and increasing power loss within the lt3743. table 4. switching frequency switching frequency (mhz) r t (k) 1 40.2 0.750 53.6 0.5 82.5 0.3 143 0.2 221 figure 12. output voltage regulation and overvoltage protection feedback connections lt3743 r2 v out r1 3743 f12 fb soft-start unlike conventional voltage regulators, the lt3743 utilizes the soft-start function to control the regulated inductor current. the charging current is 5.5a and reduces the regulated current for both the high and low regulated current states. the ss pin is latched in a discharge state until the ? rst pwm pulse and is reset by uvlo and thermal shutdown. programming switching frequency the lt3743 has an operational switching frequency range between 200khz and 1mhz. this frequency is programmed with an external resistor from the rt pin to ground. do not leave this pin open under any condition. the rt pin is also current limited to 60a. see table 4 and figure 13 for resistor values and the corresponding switching frequencies. r t (k) 0 frequency (mhz) 0.4 0.8 1.2 0.2 0.6 1.0 100 200 300 400 3743 f13 500 50 0 150 250 350 450 figure 13. frequency vs r t resistance
lt3743 19 3743fb applications information the en/uvlo pin as an absolute maximum voltage of 6v. to accommodate the largest range of applications, there is an internal zener diode that clamps this pin. for applications where the supply range is greater than 4:1, size r2 greater than 375k. thermal shutdown the internal thermal shutdown within the lt3743 engages at 163c and terminates switching, resets soft-start and shuts down the pwmgl and pwmgh drivers. when the part has cooled to 155c, the internal reset is cleared and soft-start is allowed to charge once the pwm signal is asserted. switching frequency synchronization the nominal switching frequency of the lt3743 is determined by the resistor from the rt pin to ground and may be set from 200khz to 1mhz. the internal oscillator may also be synchronized to an external clock through the sync pin. the external clock applied to the sync pin must have a logic low below 0.3v and a logic high higher than 1.25v. the input fre- quency must be 20% higher than the frequency determined by the resistor at the rt pin. input signals outside of these speci? ed parameters will cause erratic switching behavior and subharmonic oscillations. the synchronization range is 240khz to 1.2mhz. synchronization is tested at 500khz with a 200k r t resistor. operation under other conditions is guaranteed by design. when synchronizing to an external clock, please be aware that there will be a ? xed delay from the input clock edge to the edge of switch. the sync pin must be grounded if the synchronization to an external clock is not required. when sync is grounded, the switching frequency is determined by the resistor at the rt pin. shutdown and uvlo the lt3743 has an internal uvlo that terminates switching, resets all synchronous logic, and discharges the soft-start capacitor for input voltages below 4.2v. the lt3743 also has a precision shutdown at 1.55v on the en/uvlo pin. partial shutdown occurs at 1.55v and full shutdown is guaranteed below 0.5v with <1a i q in the full shutdown state. below 1.5v, an internal current source provides 5.5a of pull-down current to allow for programmable uvlo hysteresis. the following equations determine the voltage divider resistors for programming the uvlo voltage and hysteresis as con? gured in figure 14. r2 = v hyst 5.5 a r1 = 1.55v ?r2 v uvlo C 1.55 v lt3743 v in r2 v in r1 3743 f14 en/uvlo figure 14. uvlo con? guration led current derating using the ctrl_t pin the lt3743 is designed speci? cally for driving high cur- rent leds. most high current leds require derating the maximum current based on operating temperature to prevent damage to the led. in addition, many applications have thermal limitations that will require the regulated current to be reduced based on led and/or board tem- perature. to achieve this, the lt3743 uses the ctrl_t pin to reduce the effective regulated current in the led for both the high and low control currents. while ctrl_h and ctrl_l program the regulated current in the led, ctrl_t can be con? gured to reduce this regulated cur- rent based on the analog voltage at the ctrl_t pin. the led/board temperature derating is programmed using a resistor divider with a temperature dependant resistance (figure 15). when the board/led temperature rises, the ctrl_t voltage will decrease. to reduce the regulated current, the ctrl_t voltage must be lower than voltage at the ctrl_l and ctrl_h pins. lt3743 v ref r ntc r x r v r v r2 r1 (option a to d) 3743 f15 ctrl_t b r ntc a r ntc r x d r ntc c figure 15. led current derating vs temperature using ntc resistor
lt3743 20 3743fb applications information average current mode control compensation the use of average current mode control allows for precise regulation of the inductor and led currents. figure 16 shows the average current mode control loop used in the lt3743, where the regulation current is programmed by a current source and a 3k resistor. to design the compensation network, the maximum com- pensation resistor needs to be calculated. in current mode controllers, the ratio of the sensed inductor current ramp to the slope compensation ramp determines the stability of the current regulation loop above 50% duty cycle. in the same way, average current mode controllers require the slope of the error voltage to not exceed the pwm ramp slope during the switch off-time. since the closed-loop gain at the switching frequency produces the error signal slope, the output impedance of the error ampli? er will be the compensation resistor, r c . use the following equations as a good starting point for compensation component sizing: r c = f s ?l ? 1000v v o ?r s [ ], c c = 0.002 f s [f] where f s is the switching frequency, l is the inductance value, v in is the input voltage and r s is the sense resistor. for most led applications, a 4.7nf compensation capaci- tor is adequate and provides excellent phase margin with optimized bandwidth. please refer to table 6 for recom- mended compensation values. for applications where the load is not an led, please call the factory for additional compensation assistance. board layout considerations average current mode control is relatively immune to the switching noise associated with other types of control schemes. placing the sense resistor as close as possible to the sense + and sense C pins avoids noise issues and ensures the fastest led current transition time. for currents exceeding 5a, use 10 resistors in-series with sense + and sense C , with a 33nf capacitor placed as close as possible to the sense + and sense C pins. utilizing a good ground plane underneath the switching components will minimize interplane noise coupling. to dissipate the heat from the switching components, increase the area of the switching node as much as possible without negatively affecting the radiated noise. the interconnect inductance and resistance between the output capacitors and the led load directly impacts the rise time of the load current. to reduce the inductance and resistance, make the traces as wide as physically possible and minimize the trace length. table 6. recommended compensation values v in (v) v o (v) i l (a) f sw (mhz) l (h) r s (m) r c (k) c c (nf) 12 4 5 0.5 1.5 5 47.5 4.7 12 4 10 0.5 1.5 5 47.5 4.7 12 5 20 0.25 1.8 2.5 38.3 8.2 24 4 2 0.5 1.0 2.5 52.3 4.7 24 4 20 0.5 1.0 2.5 52.3 4.7 C + g m error amp modulator load r c lr s 3k v ctrl ? 11a/v c c 3743 f16 figure 16. lt3743 average current mode control scheme
lt3743 21 3743fb typical applications 12v, 20a led driver en/uvlo pwm ctrl_sel en/uvlo pwm ctrl_sel hg v in cboot v ref ctrl_l ctrl_h ctrl_t lt3743 rt sync sw lg gnd vch vcl sense + sense C pwmgh pwmgl v cc_int 100nf l1 1.0h 22f c1 330f s 3 2.5m 33nf fb 10nf 34k 4.7nf 34k d1: luminus pt120 l1: ihlp4040dzer1r0m01 m1: rjk0365dpa m2: rjk0346dpa m3, m4: si7236dp c1, c2, c3: ptpr330m9l (three in parallel) 4.7nf 82.5k 50k 50k c3 330f s 3 d1 60.4k 3743 ta02 10k 1f 2.2nf r ntc 10k 220f m1 m2 m3 m4 v in 12v output 20a maximum 1f c2 330f s 3 ss r hot 499 10 10 ctrl_sel dimming duty cycle (%) 0 90 92 94 80 3743 ta02b 88 86 20 40 60 100 84 82 80 effiency (%) v in = 12v green led ef? ciency (stepping from 2a to 20a)
lt3743 22 3743fb typical applications 6v to 36v, 2a led driver with shunted output en/uvlo pwm ctrl_sel en/uvlo intv cc ctrl_sel hg v in cboot v ref ctrl_l ctrl_h ctrl_t lt3743 rt sync sw lg gnd vch vcl sense + sense C pwmgh pwmgl v cc_int 100nf l1 10h 22f 25m fb 10nf 34k 4.7nf 34k 4.7nf 82.5k 40.2k m3 d1: luminus cbt-40 l1: mss1048-103mlb m1, m2: si7848bdp m3: si2312bds d1 m2 m1 3743 ta03 10k 2.2nf r ntc 10k 8.2f v in 6v to 36v output 2a maximum 2.2f 1f ss r hot 499 control input shunted output with ctrl_h equal to ctrl_l 6v to 36v, 2a led driver with current limited shunted output shunted output with ctrl_l at gnd en/uvlo pwm ctrl_sel en/uvlo intv cc ctrl_sel hg v in cboot v ref ctrl_h ctrl_l ctrl_t lt3743 rt sync sw lg gnd vch vcl sense + sense C pwmgh pwmgl v cc_int 100nf l1 10h 22f 25m fb 10nf 34k 4.7nf 34k 4.7nf 82.5k 40.2k d1 3743 ta04 10k 2.2nf r ntc 10k 8.2f m1 m2 m3 v in 6v to 36v output 2a maximum 2.2f 1f ss r hot 499 control input d1: luminus cbt-40 l1: ihlp4040dze10r0m01 m1, m2: si7848bdp m3: si2312bds sw 2v/div i l 2a/div ctrl_sel 5v/div i led 1a/div 20s/div 3743 ta03b sw 10v/div i l 2a/div ctrl_sel 5v/div i led 1a/div 20s/div 3743 ta04b
lt3743 23 3743fb typical applications 6v to 30v, 20a led driver with switched cathode en/uvlo pwm ctrl_sel en/uvlo pwm v cc_int hg v in cboot v ref ctrl_l ctrl_h ctrl_t lt3743 rt sync sw lg gnd vch vcl sense + sense C pwmgl pwmgh v cc_int 150nf l1 1.1h 22f 2.5m fb 10nf 34k 4.7nf 82.5k 60.4k 3743 ta05 10k 2.2nf r ntc 10k 82f m1 m2 10 m3 d1: luminus pt121 l1: mvr1261c-112ml m1: rjk0365dpa m2: rjk0328dpb m3: sir496dp c1: ptpr330m9l (three in parallel) v in 6v to 30v output 20a maximum c1 330f s 3 d1 1f ss r hot 499 control input 10 33nf switched cathode pwm dimming (100:1) 0a to 20a pwm 5v/div i led 10a/div sw 10v/div 10s/div 3743 ta05b 0a to 20a ef? ciency pwm dimming duty cycle (%) 0 efficiency (%) 60 80 100 80 3743 ta05c 40 20 50 70 90 30 10 0 20 40 60 100 v in = 12v green led
lt3743 24 3743fb typical applications 24v, 20a 3-led driver en/uvlo pwm ctrl_sel en/uvlo pwm v cc_int hg v in cboot v ref ctrl_h ctrl_l ctrl_t lt3743 rt sync sw lg gnd vch vcl sense + sense C pwmgh pwmgl v cc_int 100nf l1 1.2h m1 m2 m3 20f 470f 10 red leds 2.5m fb 10nf 24.3k 4.7nf 82.5k 20k 60.4k 316k l1: 1hlp5050fder1r2m01 m1: si7848bdp m2, m3: rjk0330dpb 3743 ta07 20k 2.2nf r ntc 10k 82f v in 24v output 20a maximum 1f ss r hot 499 10 33nf ef? ciency duty cycle (%) 0 efficiency (%) 80 90 100 80 3743 ta07b 70 75 85 95 65 60 20 40 60 100 v in = 24v 3 red leds
lt3743 25 3743fb package description ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) 4.00 p 0.10 (2 sides) 2.50 ref 5.00 p 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 27 28 1 2 bottom viewexposed pad 3.50 ref 0.75 p 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 s 45 o chamfer 0.25 p 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 p 0.05 0.25 p 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 p 0.05 5.50 p 0.05 2.65 p 0.05 3.10 p 0.05 4.50 p 0.05 package outline 2.65 p 0.10 3.65 p 0.10 3.65 p 0.05
lt3743 26 3743fb package description fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation eb fe28 (eb) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 o C 8 o 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8910 11 12 13 14 19 20 22 21 15 16 18 17 9.60 C 9.80* (.378 C .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 p 0.05 0.65 bsc 4.50 p 0.10 6.60 p 0.10 1.05 p 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
lt3743 27 3743fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 2/10 revised features and typical application updated electrical characteristics values revised values on curves g32 and g33 in the typical performance characteristics section revised the block diagram changed value in equation and made minor text edit in the inductor selection section revised table 4 values added text to average current mode control compensation and board layout considerations sections in the applications information section revised all typical applications drawings 1 3, 4 8 11 13 18 20 21 to 25, 28 b 8/10 updated electrical characteristics values and conditions revised pin functions revised block diagram changed soft-start current in operation section revised units for m1 and m2 equations removed 0.1mhz switching frequency from table 4 added text to switching frequency synchronization, shutdown and uvlo sections in the applications information section corrected m2 and m3 part numbers on typical applications drawings 3, 4 9, 10 11 12 14 18 19 24, 28
lt3743 28 3743fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0810 rev b ? printed in usa related parts typical application part number description comments lt3755/lt3755-1 high side 40v, 1mhz led controller with true color 3000:1 pwm dimming v in : 4.5v to 40v, v out(max) = 60v, dimming = 3000:1 true color pwm?, i sd < 1a, 3mm 3mm qfn16, msop16e lt3756/lt3756-1 high side 100v, 1mhz led controller with true color 3000:1 pwm dimming v in : 6v to 100v, v out(max) = 100v, dimming = 3000:1 true color pwm, i sd < 1a, 3mm 3mm qfn16, msop16e ltc3783 high side 36v, 1mhz led controller with true color 3000:1 pwm dimming v in : 3v to 36v, v out(max) = 40v, dimming = 3000:1 true color pwm, i sd < 20a, 4mm 5mm dfn16, tssop16e lt3517 1.3a, 2.5mhz high current led driver with 3000:1 dimming v in : 3v to 30v, dimming = 3000:1 true color pwm, i sd < 1a, 4mm 4mm qfn16 lt3518 2.3a, 2.5mhz high current led driver with 3000:1 dimming v in : 3v to 30v, dimming = 3000:1 true color pwm, i sd < 1a, 4mm 4mm qfn16 lt3496 triple output 750ma, 2.1mhz high current led driver with 3000:1 dimming v in : 3v to 30v, v out(max) = 40v, dimming = 3000:1 true color pwm, i sd < 1a, 4mm 5mm qfn28 lt3474/lt3474-1 36v, 1a (i led ), 2mhz step-down led driver v in : 4v to 36v, v out(max) = 13.5v, dimming = 400:1 true color pwm, i sd < 1a, tssop16e lt3475/lt3475-1 dual 1.5a (i led ), 36v step-down led driver v in : 4v to 36v, v out(max) = 13.5v, dimming = 3000:1 true color pwm, i sd < 1a, tssop20e lt3476 quad output 1.5a, 2mhz high current led driver with 1000:1 dimming v in : 2.8v to 16v, v out(max) = 36v, dimming = 1000:1 true color pwm, i sd < 10a, 5mm 7mm qfn10 lt3478/lt3478-1 4.5a, 2mhz high current led driver with 3000:1 dimming v in : 2.8v to 36v, v out(max) = 40v, dimming = 1000:1 true color pwm, i sd < 10a, 5mm 7mm qfn10 24v, 40a pulsed led driver en/uvlo pwm ctrl_sel en/uvlo pwm ctrl_sel hg v in cboot v ref ctrl_l ctrl_h ctrl_t lt3743 rt sync sw lg gnd vch vcl sense + sense C pwmgh pwmgl v cc_int 220nf l1 1h 22f 33nf m2 2 m3 m4 d1 m1 2 c1 330f 3 1.25m fb 1f 51k 5.6nf 51k 5.6nf 150k 50k 50k c3 330f 3 140k 3743 ta08 20k 1f c2 330f 3 1f r ntc 10k 220f v in 24v output 40a maximum 220f 4.7f 8 1f 1f 1nf ss 10 10 r hot 499 l1: 1hlp5050fder1r0m01 m1, m2: rjk0330dpb m3, m4: si7234dp c1, c2, c3: ptpr33om9l ctrl_sel 5v/div i led 20a/div sw 10v/div 20s/div 3743 ta08b v in = 12v 4a to 40a led current step

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